The invention relates to automatic test equipment for testing complex systems and integrated circuits. In particular, the invention relates to the generation and storage of test vectors used in automated test equipment.
Systems and the integrated circuits (ICs) or semiconductors that invariably make up the systems are continuing to evolve and become more and more complex. The complexity increases witnessed in the past and anticipated in the future have led to the extensive and widespread use of automated test equipment (ATE) for testing these systems and their constituent circuits. In fact, in some cases, system complexity has increased to such an extent that accurate and complete manual testing is either impractical or even impossible. In addition to making accurate and relatively complete testing practical in the case of complex systems, automated testing using is ATEs can and does significantly reduce the costs of producing a system and/or its constituent parts. A trend toward using ATEs for testing even simple systems and ICs has been evident for some time. Today it is fair to say that virtually all major systems and IC manufacturing lines use some form of ATE.
As illustrated as a block diagram in FIG. 1A, a typical ATE 10 comprises a central processing unit (CPU) 14, memory 12, input/output (I/O) 16 hardware, and usually some form of operator interface 18. The CPU 14 controls the operation of the ATE 10 employing a test vector stored in memory 12. The test vector, often produced by an external source 20, is transmitted to the ATE and loaded into memory 12 using the I/O hardware 16. During the automated test, the CPU 14 reads the test vector from memory and controls the I/O hardware 16 in order to affect a test of the device under test (DUT) 30. The operator interacts with the ATE through the operator interface 18. For simplicity, the system or IC being tested will be referred to hereinbelow as the DUT.
As noted hereinabove, a typical automated test by an ATE employs a test vector. A test vector is a sequence of test operations to be performed and/or test values to be applied by the ATE to the system or IC under test. In most modern ATEs, the test vector is a binary sequence owing to the overwhelming use of digital computers and memory in ATEs and the propensity for complex systems to be largely digital. Each test vector used by the ATE is normally generated by first consulting a design database or specification that identifies the functionality of the system or IC being tested. A test vector for a given DUT is generated by xe2x80x98mappingxe2x80x99 or translating the desired DUT functionality testing into the functionality testing capability of the ATE. The test vector is then typically transmitted to the ATE and stored in the ATE memory. The test vector subsequently controls the test of the DUT by the ATE.
FIG. 1B illustrates a flow chart of the steps in the conventional method of performing an automated test of a DUT using an ATE 10. The method of automated testing comprises the step of consulting 40 design specifications. The design specification defines the performance of the DUT and helps determine the tests that should be performed during automated testing. The method of automated testing further comprises the step of generating 42 a test vector. Typically the step of generating a test vector employs an apparatus or computer program called an automated test pattern generator (ATPG) that utilizes information from the design specification to generate test vectors that adequately test the DUT. In the conventional method of automated testing, the step of generating a test vector 42 is followed by a step of creating 44 a completely specified test vector. The test vector generated by the step of generating 42 typically has a number, often a large number, of so-called xe2x80x98don""t carexe2x80x99 states. The step of creating 44 a completely specified test vector assigns explicit values to the xe2x80x98don""t carexe2x80x99 states in the test vector. Often this assignment is accomplished by using a random sequence generated by a step of generating 43 a random sequence.
The step of creating 44 the completely specified test vector of the conventional method of automated testing is sometimes followed by an optional step of compressing 46 the completely specified test vector to reduce the size of the test vector. The method of automated testing further comprises the step of transmitting and storing 48 the completely specified and possibly compressed test vector in the memory 12 of the ATE 10. The ATE 10 utilizes the stored completely specified test vector in the step of testing 52 to complete the method of automated testing. If the completely specified test vector has been compressed, it must be decompressed in a step of decompressing 50 the completely specified test vector. The optional steps of compressing 46 and decompressing 50 are illustrated by dashed-line boxes in FIG. 1B.
As mentioned above, the test vector is a binary sequence. Much of following discussion assumes that the testing of digital devices with a binary test vector is without loss of generality. One skilled in the art could easily extend the concepts expressed hereinbelow to a digital test situation. The testing functionality of the ATE normally exceeds required functionality testing for a given DUT. In addition, not all possible combinations of inputs and outputs need to be tested in a typical DUT to verify that it is operational and/or to locate faults. The result is that the test vectors invariably contain a large number of unspecified or xe2x80x98don""t carexe2x80x99 states in addition to specified states (i.e. those having explicitly specified values). In most situations, there are many more xe2x80x98don""t carexe2x80x99 states in a given test vector than there are specified states.
As used herein, a specified state is an element of the test vector that is assigned a specific value as a result of mapping the DUT test functionality into ATE test functionality. A xe2x80x98don""t carexe2x80x99 state is an element in the test vector that is not specified by the DUT to ATE functionality mapping and so, can take on any value constrained only by the limits placed on an element in the test vector. For example, in the case of a binary test vector, the specified state is either a xe2x80x981xe2x80x99 or a xe2x80x980xe2x80x99, as specified by the mapping. The xe2x80x98don""t carexe2x80x99 state can be either a xe2x80x981xe2x80x99 or a xe2x80x980xe2x80x99 and is not specified by the mapping.
As discussed hereinabove, the test vector is usually constructed or generated using an apparatus or computer program known as an ATPG. For a digital case, the ATPG typically generates the test vector based on the DUT test specification using three-level logic consisting of {1, 0, X} where the X is a xe2x80x98don""t carexe2x80x99 value indicating a xe2x80x98don""t carexe2x80x99 state. Thus, the test vector is initially filled with a sequence of xe2x80x981xe2x80x99s, xe2x80x980xe2x80x99s and xe2x80x98Xxe2x80x99s. The method defining how the ATPG decides to construct a test vector is beyond the scope of this discussion. In general, however, the ATPG generally attempts to construct a test vector that maximizes the probability of finding all potential faults while simultaneously minimizing the test time for a given DUT.
The test vector, when transmitted to and stored in the ATE memory, must have an unambiguous value. Therefore, the ATPG must assign a deterministic value to all xe2x80x98don""t carexe2x80x99 states. Typically the assignment of a value to a xe2x80x98don""t carexe2x80x99 state by the ATPG is accomplished using a random sequence generator. The random sequence generator xe2x80x9cfillsxe2x80x9d the xe2x80x98don""t carexe2x80x99 states of the test vector with random values. For example, in the case of a binary test vector, the specified states are assigned the appropriate value, either xe2x80x981xe2x80x99 or xe2x80x980xe2x80x99 and then a random sequence generator that generates a random binary string is consulted to fill the xe2x80x98don""t carexe2x80x99 states.
FIG. 2 illustrates an example of a typical test vector, as generated by the produce a conventional, completely specified test vector. In the first line 81 of FIG. 2, a sequence generated by the ATPG, including xe2x80x98don""t carexe2x80x99 states, is depicted. In the next line 82, a random binary sequence, as might be generated by the random sequence generator, is shown. Finally, in the last line 83 of FIG. 2, the completely specified test vector, as it exists after replacing the xe2x80x98don""t carexe2x80x99 states with corresponding bits from the random sequence, is illustrated. It is the last sequence of the last line 83 of FIG. 2 that is conventionally transmitted to and stored in the memory of the ATE. The filled test vector is referred to herein as a xe2x80x9ccompletely specifiedxe2x80x9d test vector to distinguish it from the test vector including xe2x80x98don""t carexe2x80x99 states.
Conventionally, the completely specified test vector is transmitted to and stored in the memory of the ATE. Test vectors can be very large and can occupy significant amounts of memory in the ATE. In many cases, memory necessary to store the test vectors in the ATE may account for as much as 50% of the cost of the ATE. Moreover, even when ATE memory cost is not a significant factor, the time associated with transmitting the test vector to the ATE memory can be significant. Additionally, a device may require more memory for storing test vectors than is available in a given ATE. Therefore, it is advantageous to consider approaches to compressing the test vector to minimize the amount of memory needed for a given test vector.
Conventional test vector compression approaches include (i) using some form of encoding on the test vector and (ii) breaking the test vector into a pair of vectors, one for data bits and another for containing a control program. The first of these two approaches borrows from conventional compression technology used in such technology areas as disk drives and digital communications. A compression algorithm is applied to the completely specified test vector. The compression algorithm reduces the size of the completely specified test vector by removing redundancy typically using an encoding technique. The compressed test vector is then transmitted to and stored in the ATE memory. During execution of the test by the ATE, the compressed test vector is decompressed using a reverse of the compression algorithm used for compression. Compression of binary test vectors of as much as 50% is often achieved by this approach. One skilled in the art would readily identify a number of applicable compression algorithms for compressing completely specified test vectors.
The second approach to test vector compression employs an algorithm to segregate the completely specified test vector generated by the ATPG into two or more, smaller vectors that when taken together are smaller than the original completely specified test vector. These two smaller vectors are generally distinguished in that one contains so called xe2x80x9cdataxe2x80x9d while the other contains xe2x80x9cinstructionsxe2x80x9d. The instruction vector used in conjunction with the data vector enables the reconstruction of a completely specified test vector equivalent to that originally generated by the ATPG. Of course, to use this approach for compressing a completely specified test vector, the ATE must be capable of xe2x80x9cexecuting the instructionsxe2x80x9d. Enabling the ATE to execute the instructions is not fundamentally different from executing a decompression algorithm required by the first approach to compression. G. Lesmeister, U.S. Pat. No. 5,696,772, discloses an example of this form of compression.
Typically, ATEs provide an ability to execute fairly general software programs within the central processing unit (CPU) of the ATE. Therefore, the requirements for decompression placed on the ATE by the above described compression approaches do not pose a significant limitation. It should be noted that in both cases of test vector compression described hereinabove, the ATPG generated test vectors processed by the compression algorithms are completely specified test vectors.
Accordingly, it would be advantageous to have a method for generating and storing a test vector for use in an ATE that significantly reduces the amount of memory required to store the pattern. In addition, it would be desirable that such a method takes advantage of the xe2x80x98don""t carexe2x80x99 states typically found in the test vector prior to complete specification to facilitate compression of the test vector. Such a method would significantly improve the average efficiency of compression thereby solving a long-standing need for test vector memory reduction in the area of ATE testing.
The present invention provides a novel test vector compression method. The test vector compression method creates a compressed test vector for use in conjunction with automated test equipment (ATE).
In one aspect of the present invention, a method of compressing a test vector is provided. The method of compressing comprises the steps of generating the test vector having a sequence of elements, and producing a random sequence of elements having at least the same number of elements as the test vector. At least one element of the test vector comprises a xe2x80x98don""t carexe2x80x99 value indicating a xe2x80x98don""t carexe2x80x99 state. The method of compression further comprises the steps of sequentially segmenting the test vector into segments of the test vector elements and similarly segmenting the random sequence into corresponding segments of the random sequence elements. Each segment of the test vector is compared to a corresponding segment of the random sequence to determine whether the corresponding segments match or do not match. When a match is found, a first flag value is sequentially inserted into a first sequence. When a mismatch is found, a second flag value is sequentially inserted into the first sequence as well as the elements of the mismatched test vector segment. The compressed test vector is created from the first sequence when all of the segments have been compared.
The compressed test vector produced by the method of the present invention can be transmitted to and stored in the ATE memory. Further, the method of compressing according to the invention eliminates the step of specifying the xe2x80x98don""t carexe2x80x99 states prior to the compression step. Advantageously, the storage requirements of the compressed test vector produced by the method of the present invention are much smaller than those of a completely specified test vector conventionally used in ATE.
In one embodiment, the method of compressing a test vector further comprises the step of decompressing the compressed test vector to produce a decompressed test vector that is the same as the completely specified test vector conventionally used by ATE. The ATE can be adapted for decompression in accordance with the method of the invention. Decompression comprises the steps of examining the compressed test vector sequentially for the first flag value and the second flag value. When a first flag value is found, the elements of the corresponding random sequence are inserted into a second sequence. When a second flag value is found, the elements of the compressed test vector that follow the second flag value are inserted into the second sequence. The decompressed test vector is produced from the second sequence after the entire compressed test vector has been examined. The decompressed test vector is a completely specified test vector, such as that conventionally used in ATE.
In another aspect of the present invention, a method of compressing and decompressing a test vector that has a sequence of elements is provided. The method comprises the step of producing a random sequence of elements having at least a same number of elements as the test vector. The method further comprises the steps of sequentially segmenting the test vector into segments of the test vector elements, wherein at least one element of the test vector comprises a xe2x80x98don""t carexe2x80x99 value, and similarly segmenting the random sequence into corresponding segments of the random sequence elements. The method further comprises the step of comparing each segment of the test vector to corresponding segments of the random sequence to determine whether the corresponding segments match. The test vector is compressed by inserting one flag value for the matched corresponding segments and another different flag value for the corresponding segments that do not match (mismatched). The compressed test vector is then decompressed into a completely specified test vector based on the different flag values.
In one embodiment of the method of compressing and decompressing a test vector, the step of compressing comprises the step of sequentially inserting a first flag value into a first sequence for each segment of the test vector that matches a corresponding segment of the random sequence. Compression further comprises the steps of sequentially inserting a second flag value into the first sequence for each segment of the test vector that does not match a corresponding segment of the random sequence followed by inserting the elements of the mismatched test vector segment into the first sequence. The compressed test vector is created from the first sequence when all of the segments have been considered.
In another embodiment of the method of compressing and decompressing a test vector, the step of decompressing comprises the steps of generating another random sequence of elements that is the same as the random sequence produced in the step of producing; sequentially inserting the corresponding elements of the other random sequence into a second sequence for each flag value indicating a match; and sequentially inserting the elements of the compressed test vector that follow each flag value indicating a mismatch into the second sequence. The decompressed test vector is created from the second sequence when the entire compressed test vector has been considered. The decompressed test vector is a completely specified test vector.
According to the invention, corresponding segments match when each element of the test vector segment matches the corresponding element of the corresponding random sequence segment. Further, an element of the test vector segment matches a corresponding element of the random sequence segment when the respective element has the same value or when the element of the test vector segment has the xe2x80x98don""t carexe2x80x99 value. The compressed test vector is transmitted to and stored in the memory of the ATE. Advantageously, in part because of the number of xe2x80x98don""t carexe2x80x99 states typically found in ATPG generated test vectors, the compressed test vector requires considerably less storage space in memory as compared to a completely specified test vector that would have been generated from the test vector using conventional methods. Conventional ATEs can perform the step of decompression, provided that the ATE is modified to support the decompression steps of the invention.